A Simulink® model for Direct Sequence Spread Spectrum
(DSSS) receiver is presented. Using data-path size as an
additional parameter in the model blocks made it possible
to do the hardware optimization of the receiver on the
block-by-block basis. The effect of the round-off errors to
the bit-error rate (BER) of the receiver is quantified for
each block in the model. Different functional parts of the
receiver, such as analog-to-digital converter (ADC), digital
down-converter (DDC), matched filter, are shown to have
different sensitivity to the data-path size. Using
multivariable optimization, one can use the model to
minimize the hardware implementation with respect to the
BER
Keywords
Digital down-converter, matched filter, analog-to-digital
converter round-off error
DSSS Receiver Using Simulink and Hardware Optimization
