5-V Logic Circuits

Designers of digital systems are constantly confronted with the problem of synchronizing two systems that operate at different frequencies. The problem is usually resolved by synchronizing one of the signals with the local clock generator using a flip-flop. But such a solution, of necessity, leads to a violation of the operating conditions for the flip-flops as defined in the data sheets, i.e., in these cases, the setup time and hold time are not maintained. Therefore, a flip-flop can go into a metastable state, endangering the operability of the circuit and, thereby, the reliability of the whole system. The purpose of this report is,
first, to acquaint designers with the phenomenon of metastability in dynamic circuits (flip-flops) and, second, to look at test results on the more common bipolar, CMOS, and BiCMOS circuit families. Using these data the designer can determine the influence of metastable states in an application and take any necessary countermeasures