Electromigration (EM) is themain reliability concern and will
become a more limiting factor of IC designs. The power generated by self-heating effect in interconnects only contributes a small part of the chip power consumption. However, the impacts of thermal effects on the reliability of interconnects are serious. Therefore, EM must be addressed together with a thermal reli- ability modeling and is recognized in the International Technology Roadmap for Semiconductors (ITRS) 2002 update as one of the difficult challenges [1]. In order to diagnose the thermal reliability and improve the design quality, an efficient chip-level three-dimensional (3-D) thermal simulator is crucial to success for the VLSI designs
There are some challenges for the thermal modeling and simulation. First, the uniform heat distribution in a chip does not guarantee the uniform temperature profile due to the complex 3-D nature of heat spreading and the complicated boundary conditions. Simulation runtime and memory usage are another issues due to the large size of integrated circuit systems. Several approaches have been proposed. A full-chip thermal simulation was presented in [5] solving function-block size problem. The
finite difference method (FDM) with equivalent RC model has been presented [6] [7]. However, due to the large size of matrix, the direct matrix-solving algorithms have runtime and memory usage problems for large scale systems. A thermal simulation method based on model reduction was presented to improve the runtime [8]. However, the bottleneck in such method is that the number of input sources can cause big Krylov subspace
SPICE-Compatible Thermal Simulation
